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crc_32_16
- crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
ethernet.tar
- 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
crc
- 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
CRC
- CRC和线性码程序 可能对初级学习有用 希望能够好好利用-CRC
crc
- CRC-16 VHDL Source Code
crc_verilog_xilinx
- CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
CRC_outputlogic
- custom crc generater(verilog/vhdl)
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
crc
- For implementing the CRC in verilog or VHDL