搜索资源列表
H.265_TMS320C64X_DEMO
- ZPAV（小名H265），凝集 形态，分形，模糊，小波，数字图象处理学 等数学精华， 我 感受到了她的威猛的能量，听到了她的呐喊！她如春雷， 震撼着 单薄数学（DCT+ME+HUFFMAN等）的MPEGxx和H26xx的古老统治！ ZPAV (H.265) 基本算法 ：V0,V6 用了 二维小波；V8 用了 三维小波；V9 用了 四维小波； P帧（ME） 使用了 小波域运动估计；声音(A0,A6,A8,A9), 运动矢量（MV） 使用了 广义小波。 Z
dct
- 2维DCt源码，可以实现8乘8点数据的2维DCT变换
2DImageFilterByVHDL
- 用VHDL语言编程实现2维图像的滤波算法，简单精辟-VHDL programming language used to achieve 2-D image filtering algorithm, simple brilliant
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
ARM_DCT
- DCT library ADM C ADS 1.2
DCT2
- 2 维 DCT的VHDL实现以及 测试代码 ， -2-D DCT of the VHDL implementation and test code
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
shift_arr
- This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.