搜索资源列表
sc16is752
- sc16is752 device s firmware source code SC16IS752 is Dual UART with I2C/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
4432_DKDBx_(TXRX_Switch_470M)(1)
- GT033-TRX 是一款低成本的ISM 频段FSK 收发模块, 可工作在240--930MHZ 中任意频点。功率可以最大配 置为20dBm（si4432）,13dBm(si4431),接收灵敏度可达-118dBm,64 字节 TX/RX FIFOS,内置温度传感器， 8 位模数转换器,3 个I/O。支持跳频工作模式。可提供一个SPI 接口，通过MCU 设置就可调整各种参数（发 射功率.中心频点.带宽等）。无需外加功放电路就可实现远距离无线数据传输.-GT033-TRX is a l
fifos
- 通用的ｆｉｆｏ设计，带有ｔｅｓｔｂｅｎｃｈ，和ｄｅｓｉｇｎ＿ｆｌｏｗ-Fifo generic design, with a testbench, and design_flow
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt gene
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
FIFOMXN
- 该VHDL描述的是一个简单的先进先出存储器-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
generic_fifo_yh
- Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
SPI
- Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous comm
SI4463
- SILABS新推出SI4463完整DEMO板原理图、PCB图、DEMO程序下载。传输距离1000~2000米 SILABS新推出EZradioPRO系列RFIC:SI4432,适合长远距离的无线数据传输应用.其发射功率+20dbm,接收灵敏度-116dbm,通讯距离2000米 SI4463特点 频率范围= 119–1050 MHz 接收灵敏度 = –126 dBm 调频模式 (G)FSK and 4(G)FSK OOK and ASK 最大输出功率 +20 d
UART2_4F120
- 从运行超级终端的计算机上运行测试UART0并实现双向数据转移。这一次，我们使用了中断和FIFO。-Tests the UART0 to implement bidirectional data transfer to and from a computer running HyperTerminal. This time, interrupts and FIFOs are used. U0Rx (VCP receive) connected to PA0 U0Tx