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rng
- verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的
lfsr
- 此实验介绍了伪随机序列的产生原理，并用verilog语言将其编码实现，有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
profiles
- source code of counter,ram,lfsr etc
BIST
- A simple BIST in VHDL. It contains a LFSR with an SISR.
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
lfsr
- linear feedback shift register verilog code
lfsr
- simple PRBS generator using verilog hdl
LFSR_UPDOWN_Verilog
- the LFSR up/down counter are designed in a verilog module easy to implement in any counter operation.
RSN
- “Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce a
LAB-16
- 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
CRC_test
- 基于verilog编写的CRC校验程序，采用LFSR电路实现。-CRC verilog
verilog-lfsr-updown-counter
- Verilog 8 bit LFSR Up-Down Counter
LFSR
- Verilog code for an 8-bit LFSR
HWL_PRBS_GEN
- Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. PRBS. Verilog language
LFSR
- 这是基于FPGA开发板NEXTS3的一个verilog程序，是一个线性反馈移位寄存器LFSR,可用来生成伪随机数-This is based on the FPGA development board NEXTS3 a verilog program, is a linear feedback shift register LFSR, can be used to generate pseudo random Numbers
hidejj
- 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
pseudo_random
- 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
BIC
- this project for adaptive schme techniques by using LFSR design projects