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These_Pelcat
- Rapid Prototyping and Dataflow‐Based Code Generation for the 3GPP LTE eNodeB Physical Layer Mapped onto Multi‐Core DSPs
CHANNEL_ESTIMATION_PROJECT
- 基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来-Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it
conv_encoder
- TD-LTE中(3.1.7)咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code