搜索资源列表
Lesson09_LCD
- s3c44b0X,LCD测试程序，分别进行黑白、4级灰度、16级灰度和256色伪彩屏测试-s3c44b0X, LCD testing procedures were black and white, gray 4, 16 and 256 gray pseudo-color screen test
一些VHDL源代码
- 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
s_EOS
- 时间触发式单片机最小系统，一直在用，伪多任务-time-triggered smallest SCM system has been in use, pseudo-multi-tasking
GUI(LCD-DRIVER)
- 开发环境为ADS1.2 ARM用户界面开发接口程序 GUI 提供了最基本的画点 线 圆形 圆弧 椭圆形 矩形 正方形 填充等功能 较高级的接口功能有 ASCII显示 汉字显示 图标显示 窗口 菜单等 支持单色 灰度 伪彩 真彩等图形显示设备-ADS1.2 development environment for the development of ARM user interface GUI interface to provide the most basic point of
serial_produce
- 设计一个能够自启动的24-1的伪随机码（111101011001000）发生器。 设计一个序列信号发生器，产生一个011100110011序列码。 实现序列1110100。测试序列码波形 个人比较欣赏第二种方法 -to design an 24-1 since the start of the pseudo-random number (111101011001000) generator. Design of a signal sequence generator to pro
cesffffsfesfesf
- 产生级数为4的M序列，P1输入4个初值，在数码管上显示出来，单片机模拟产生伪序列码-produce series for the M-4 sequence, P1 four initial input, the digital control on the show. SCM simulation of pseudo-sequence code
suij
- 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
weishujituanfashengqishejishili
- 伪随机图案发生器设计实例，也是可以拿来用的，扩频和跳频通信有用-pseudo-random pattern generator design examples, and can be used with the frequency hopping spread spectrum communication and useful
omf
- 伪随机序列编码源程序-an encode program of pseudo-random sequence
ldpcber
- This LDPC software is intended as an introduction to LDPC codes computer based simulation. The pseudo-random irregular low density parity check matrix is based on Radford M. Neal’s programs collection, which can be found in [1]. While Neal’s collecti
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Pseudo_Random_Num_Generator
- The file included is the source code for Pseudo Random Generator
pseudo-randomcodegenerator
- VERILOG语言编写的伪随机码产生器，可以ISE中编绎调试-VERILOG language of pseudo-random code generator, you can unravel ISE in debugging code
pseudo-random-sequence-generator-
- 利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
Pseudo-random-sequence-generator
- 通过MATLAB的SIMULINK模型设计，实现伪随机数的序列发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization of pseudo random sequence generator, and through the DSP BUILDER of SIGNAL COMPILER converted into Quartu
Pseudo-random
- 伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
Matrix-pseudo-inverse
- 矩阵求伪逆，在图像，机器人，压缩文件方面都有很大的用处-Matrix pseudo-inverse, compressed files have great usefulness in the image, the robot
Pseudo-Random
- Pseudo Random Sequence Generator Code and Tutor
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator