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伪随机序列编码源程序-an encode program of pseudo-random sequence
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verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
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此实验介绍了伪随机序列的产生原理，并用verilog语言将其编码实现，有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
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精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
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伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
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伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
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本文设计了一种简捷而又高效的伪随机序列产生方法，最后通过统计对比，说名这种方法产生的随机序列不仅周期长
还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence gen
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伪随机序列应用verilog设计.rar-Application of pseudo-random sequence verilog design.rar
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8*8乘法器设计
伪随机序列发生器
PS2键盘设计
均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
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基于FPGA的伪随机序列误码率检测，包括随机序列的发生，随机序列的接收统计。-FPGA-based pseudo-random sequence of bit error rate testing, including the occurrence of random sequence, random sequence to receive statistics.
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伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
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利用一种伪随机数生成的新方法 ———超素数法，在单片机的P1.6口产生周期为498的伪随机序列。-Pseudo-random number generator using a new method--- law of prime numbers, generated in the microcontroller ports P1.6 period of 498 pseudo-random sequence.
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关于编译的一个3位伪随机序列源文件，简单实用，适合作例题看！-Compiled on a three pseudo-random sequence of source files, simple and practical, suitable for example to see!
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利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
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通过MATLAB的SIMULINK模型设计，实现伪随机数的序列发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization of pseudo random sequence generator, and through the DSP BUILDER of SIGNAL COMPILER converted into Quartu
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伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
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8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
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Pseudo Random Sequence Generator Code and Tutor
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伪随机序列应用设计，应用与产生伪随机序列，FPGA实现-Pseudo-random sequence application design, application and generate a pseudo-random sequence, FPGA realization
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STC89C52单片机上已成功实现，利用计数器产生伪随机数列，基本可以满足要求-STC89C52 single-chip has been successfully achieved, the use of counter generates a pseudo-random sequence, to meet the basic requirements
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