搜索资源列表
一些VHDL源代码
- 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
ceshixiangliang
- vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples --- corresponding Adder test vector (test bench). Txt
freq_cnt
- 利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期
RS232uart(VHDL)
- 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
FFT VHDL
- VHDL实现FFT测试文件
uart全套vhdl程序
- uart全套vhdl程序 测试过，完全能用
VHDL38decoder
- VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序-38 decoder VHDL language implementation, including program source code file, there are testbench test procedures
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
div
- FPGA调试程序，测试程序，分频率。可以用于FPGA的初学使用-FPGA debugger, test procedures, sub-frequency. FPGA can be used for the beginner to use
frequency_measured_amplitude_phase_measurement
- 2008年北京市大学生电子设计竞赛程序源代码[测频率，测幅值，测相位]。进过竞赛测试性能良好，获奖作品-Beijing 2008 Undergraduate Electronic Design Contest source code [test frequency, measured amplitude, phase measurement]. Progressive had a good race to test the performance, winning entries
VHDL
- 数码管显示，温度传感，红外感应，流水灯蜂鸣器，PS2,RS232的相关VHDL程序，已经在MAX-IIEPM570开发板上测试成功-Digital display, temperature sensor, infrared sensor, water lights buzzer, PS2, RS232 relevant VHDL procedures have been developed at MAX-IIEPM570 the success of on-board test
CordicNCO
- 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
interleaver
- 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
chap6
- 10个VHDL的经典实例，加法计数器中的进程，任务举例，测试程序，函数-10 VHDL classic example of the counter in the process of addition, tasks for example, test procedures, functions. . .
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test benc
DWT-VHDL
- 小波变换的VHDL代码，内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.
test_vector
- 教你如何写测试向量，也是刚学会的，用VHDL写的，可以参考-Teach you how to write test vectors, but also a newly learned, written with VHDL, refer to
adv7123测试程序-vhdl
- 基于adv7123芯片的彩条测试程序，vhdl语言编写，下载即用。(Color test program based on adv7123 chip)
Profibus DP - VHDL BUS Model
- Profibus DP VHDL总线模型设计,包含主站和从站VHDL设计代码和测试代码