搜索资源列表
flash
- fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
ram_r_w
- 用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language descr iption of the memory read and write, user-friendly, simple and practical.
ram
- 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
pci_t
- verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
r_w_flash
- FPGA高速完成AD采集回来的数据进行高速读写FLASH存储-AD Acquisition completion of FPGA high-speed data back to high-speed read and write FLASH memory
rom
- 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
LPC2DDR2
- Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
led_control
- 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。 直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimenta
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
xapp944_source
- 主要用来实现FPGA控制nand flash存储器的读写控制，是公司网站提供-FPGA is mainly used to achieve control of read and write nand flash memory control, is the company website
sdram_controller_latest.tar
- sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is me
Audio_Reader_Flash_DE2
- This an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
nansflash
- NANDFlash存储器作为一类非易失性存储器，具有功耗低、读写快、容量大、成本低、抗震性好等优点而被广泛应用于各种嵌入式系统。 - The NANDFlash memory takes a kind of nonvolatile storage, has the power loss to be low, the read-write is quick, the capacity is big, the cost is low, the anti-knocking property go
module-Temperature
- DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据
stack_16x8
- VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out
MP3-coder
- In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read t
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,