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Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
UART.rar
- 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5,The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
i2c_ip.zip
- I2C的ip核，Verilog实现，可以直接用在你的项目中。I2C是一种简单实用的通讯协议。,I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol.
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
APB
- It s the verilog source code for AMBA APB 2.0 Slave
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
Verilog-vga
- 基于Verilog的VGA显示汉字、字符的例子以及vga资料-Verilog' s VGA display Chinese characters based on the character of the examples and information vga
105230308VerilogHDLcoding
- verilog的非常好的材料，是verilogHDL编码风格的总结。-Verilog s very good material is a summary of verilogHDL coding style.
VDHL
- Verilog的135个经典设计实例，直流电机控制，游戏机，三态总线，加法器，锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
sci_module
- verilog编写的串口模块，可以直接使用，已经成功用于产品上了。-UART by verilog.
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
Verilog-based-video-capture-source
- 基于XILINX的XST3开发板的视频采集源码，代码详细，已经测试通过-XILINX' s XST3 development board based on the video capture source code in detail, has been tested
Verilog数字系统设计教程(第2版)
- 适合学习fpga的童鞋们，verilog语言数字系统设计，一本很不错的学习资料。(Suitable for learning fpga children's shoes, verilog language digital system design, a very good learning materials.)
Verilog HDL
- Programming fpga's.
verilog dct
- 其使用模块的代码风格来编写，能够8点dct的转换(Its use of the module's code style to write, to 8 dct conversion)
Verilog黄金指南中文版
- verilog语言资料，很有效的，比夏雨闻的要好用易懂，希望有帮助(Verilog language data, very effective, better than Xia Yu's smell, easy to understand, and I hope it helps.)