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AES_RTL
- 使用Verilog HDL 實現AES硬體加解密
comp1
- 实现了加密狗的功能，完成此功能用的硬件描述语言，verilog hdl 在各方面是最好的，欢迎下载。-fpga aes
AES
- 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
AES
- 这是一个AES加密算法的程序，适用verilog hdl语言写的-A AES ALGORITHM
aes-master
- aes master by vhdl code and decode
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
aes-project-master
- aes project vhdl FPGA