搜索资源列表
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
comp1
- 实现了加密狗的功能，完成此功能用的硬件描述语言，verilog hdl 在各方面是最好的，欢迎下载。-fpga aes
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
aes
- AES FPGA verilogHDL实现(AES hardware implementation)
AESj 加密解密Verilog
- 128位AES加密解密，可以在FPGA上实现