搜索资源列表
AMBA
- SystemC写的AMBA 3.0 AXI总线事物级TLM模型 正在调试。有详细实验报告说明。-AMBA 3.0 AXI TLM SystemsC
AMBA-Specification-Rev-2.0
- AMBA2.0总线协议详细介绍，共230叶英文资料-AMBA2.0 bus protocol details, a total of 230 leaves information in English
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
lab1
- AXI-Lite bus with SPI on System C
AMBA_AXI-bus
- ARM AMBA AXI总线原理分析，详细说明了AXI总线原理；-ARM AMBA AXI bus details, details the AXI bus principle
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
axi_ad9361
- AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
cpu_uart_leds_ip
- 基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
emif2axi
- emif 接口转axi总线,测试功能正常使用，不包含仿真文件(EMIF interface to Axi bus, test function is in normal use, does not contain simulation files)