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bch_encoder_decoder
- bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
brcm_nand_ecc
- BRCM 平台ECC算法(C语言),该算法可以产生3字节的ECC,每512字节一组-BRCM NAND Flesh Memory ECC Encoder (Hamming code and BCH codes)
bch-coding
- In this project, we are implementing the error detection and correction using BCH code (Bose Chaudhuri Hocquenghem). Using VHDL and targeted on FPGA for synthesis of the code. The encoder and decoder combine called as a codec.
Bch15_7
- BCH ENCODER DECODER -BCH ENCODER DECODER
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
bch3
- BCH编码、译码器，支持参数化使用，从多项式生成、编码到解码，全都有。-BCH encoder decoder
bch_dec_enc_dcd
- 关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现-On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)