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  1. crcm

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  2. crc 校验,vhdl源码,经仿真能正常运行,供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1023
    • 提供者:fangliang
  1. CPU_Architecture

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  2. Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-09
    • 文件大小:2388732
    • 提供者:Amit Adoni
  1. CRC

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  2. CRC循环校验码的生成。文件里是(40,32)的校验码生成电路,采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:142933
    • 提供者:李雪茹
  1. CRC-Parallel-Computation

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  2. 用软件实现CRC校验码计算很难满足高速数据通信的要求, 基于硬件的实现方法中, 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础, 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:205611
    • 提供者:Geer
  1. CRC

    0下载:
  2. 赛灵思的循环冗余校验(CRC),内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the modul
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:211334
    • 提供者:我是谁
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