搜索资源列表
CIC.rar
- cpld/fpga积分梳状滤波器(CIC)设计,cpld/fpga Integral comb filter (CIC) design
Echo
- dsp上实现的音频经典混响算法,四个梳状滤波加两个全通滤波器实现-dsp audio to achieve the classic reverb algorithms, 4 comb filter plus two all-pass filter to achieve
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
shuzhuanglvboqi
- 给出了梳状滤波器的编写代码,用于数字信号处理中的滤波器设计-Gives the comb filter to write code for digital signal processing filter design
digitaldownconversionbygpga
- 研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器和级联半带滤波器的多级抽样频率算法。-Extraction of the high-powered digital down-conversion design, the focus of a cascaded integrator comb filter based on cascaded half-band filter and the multi-level sampling frequency algorithm.
cic32
- cascaded integrator comb filter 32 verilog code-cascaded integrator comb filter 32 verilog code
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
cic3_decimator
- 积分梳状滤波器(CIC)设计，解释很清晰的，希望对大家有所启发-Integrator comb filter (CIC) design, explained very clearly, we hope to be inspired. ...
cic_core
- cic积分梳状滤波器的verilog代码-the cic integral comb filter verilog code
fir
- 积分梳状滤波器(CIC)设计；,有详细的步骤-Integrator comb filter ( CIC ) design
JIFENLBOQI
- 通过verilog hdl语言完成对积分梳妆滤波器的设计-By verilog hdl language used to complete the design of the integrator comb filter
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
MultCIC
- 三级梳状积分CIC滤波器的FPGA实现代码，包括积分模块，抽取模块和梳状模块以及顶层模块的实现代码-Three integral CIC comb filter FPGA implementation code, including the integration module, extraction module and a comb and a top-level module module implementation code
CIC_filter
- 三级级联梳状滤波器（CIC）的verilog实现。顶层模块top_moduole下面包含三个子模块，积分模块integrated，抽取模块decimate和梳状滤波器模块comb，已验证可综合通过并实现CIC功能-Three-level cascade comb filter (CIC) verilog implementation.Top-level module top_moduole below contains three child module, integral module in
CIC_verilog
- 采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块-Using verilog to achieve three CIC decimation filter, the input 8-bit data output 26-bit data, the use of finite state machines for sampling, including the integrator and comb to im
ex_15
- CIC积分梳状滤波器由一个积分器和一个梳状滤波器组成，其特点就是简单、便于处理，运算速度快-CIC CIC filter consists of an integrator and a comb filter, whose characteristic is simple, easy to handle, fast operation
cic10_sec5
- 抽取因子可调，四级梳状滤波器，在数字下变频中会使用到(The decimation factor is adjustable, and the four stage comb filter is used in digital down conversion)
CIC
- 包括地址产生单元、数据查询单元（可以重新初始化rom中的数据，由matlab产生.coe文件替换）、积分单元、抽取单元、梳状滤波单元，对于初学者很有帮助(Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb fi