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卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
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用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3) - Convolutional Codes.
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提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the
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卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
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verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
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convolutional encoder vhdl code, rate 1/2, k=3
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将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
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卷积码编码，用veriolog实现一个（2,1,3）卷积编码-Convolutional coding, with veriolog implement a (2,1,3) convolutional code
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2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过--(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform
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卷积码编码与维特比解码 当K为7 时 供大家参考-convolutional encoding and Viterbi decoding with k 1 2 7 rate
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本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的编码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the (2,1,6) convolutional code encoding. Source and for the simulation of the test file inside
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本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside
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卷积码是深度空间通信系统和无线通信系统中常用的一种差错控制编码。它克服了分组码由于以码块为单位编译码而使分组间的相关信息丢失的缺点。（2，1，8）卷积码在2G、3G通信系统-The convolutional code is used in deep space communication system and a wireless communication system an error control coding. It overcomes the block code and the
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(2,1,3)卷积码编码，硬判决译码；编码是matlab语言，译码是verilog语言-(2,1,3) convolutional code encoding, hard decision decoding coding is matlab language, decoding is verilog language
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(2,1,3)卷积码编码，软判决译码；matlab语言编码；verilog语言译码；-(2,1,3) convolutional code encoding, soft-decision decoding matlab coding verilog decoder
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This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutional encoder in xilinx virtex-5
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卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
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