搜索资源列表
ethernet.tar
- 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
CRC_32
- 用verilog语言实现的的的32位CRC生成与检验的代码-The 32bits CRC using hardware describe language of verilog
crc
- 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
CRC
- CRC和线性码程序 可能对初级学习有用 希望能够好好利用-CRC
crc_verilog_xilinx
- CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
PCK_CRC16_D8
- VERILOG的CRC代码,节约资源,高效.欢迎提意见-good verilog for crc,is good for fpga.welcome to down
CRCecoder
- CRC 编码的Verilog语言，高手的作品，放心下-CRC-coded Verilog language, master' s works, rest assured that the next
Desktop
- crc校验码verilog代码，24bits，按原理写的代码-cyclic redundancy check 24 bits verilog
crc_verilog_xilinx
- verilog 代码的循环冗余校验crc实现的源程序，请大家指教-verilog crc
CRC
- CRC校验参考设计Verilog代码 包括所有代码-Verilog code for CRC check reference design includes all the code
CRC-32
- 一个关于32位循环冗余校验的verilog代码-A 32-bit cyclic redundancy check on the verilog code
gen_crc
- 任意位宽，任意多项式，并行CRC生成verilog代码脚本-CRC verilog gen scr ipt, for any width of data input
crc_tool
- 用c编写的自动生成并行crc处理的verilog代码的工具-Automatically generate the verilog code to parallel crc processing tools written with c
crc16-
- 本文档描述了一种CRC校验的方法，开发语言为verilog。程序自己写的，包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
CRC
- CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc16_d8
- 此代码采用Verilog语言实现8位CRC校验功能，采用CRC-ITU标准制定的CRC16校验-This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards