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CRC-Verilog
- 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
crc_verilog_xilinx
- 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
jjm
- 用Verilog实现的crc16编码器，可以实现任意长度帧的发送信息的crc无失真编码-Implemented with Verilog crc16 encoder can send frames of any length lossless coding of information crc
crc16-
- 本文档描述了一种CRC校验的方法，开发语言为verilog。程序自己写的，包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
jiaoyan
- Verilog编写的crc16校验程序，为大家通信校验提供一种可靠的方法-Verilog prepared crc16 checksum procedure for everyone to provide a reliable communication method validation
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
CRC16_V
- 基于Verilog的CRC16实现，已在altera FPGA验证通过-Based on the CRC16 Verilog implementation, has been verified in FPGA Altera.
sd_crc7_c16
- sd crc7 crc16 校验 verilog实现-sd crc7 crc16 verilog
crc16_d8
- 此代码采用Verilog语言实现8位CRC校验功能，采用CRC-ITU标准制定的CRC16校验-This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards
crc_unit_16
- 用verilog语言实现CRC16校验，已通过仿真验证。-Use verilog language implementation CRC16 calibration, was validated by simulation
crc16
- verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)