搜索资源列表
68013FIFOIN
- Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序，实际测试可用。可以直接跟上位机连接，传输数据。
T2_USB_IN.rar
- usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言,CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
CY7C68013.rar
- USB2.0的Verilog实现，含有完整的FPGA代码,Use Verilog to implement the USB2.0 protcol
USB_kz
- 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
cy7c68013fpga_code
- cy7c68013的fpga配置代码，verilog语法-cy7c68013 the fpga configuration code, verilog syntax
FPGA-port_Verilog_HDL
- CY7C68013与FPGA接口的Verilog HDL实现，经过本人实验检验过的，-CY7C68013 and FPGA interface Verilog HDL realize the experiment after I test
CY7C68013andFPGAinterface
- CY7C68013与FPGA接口的Verilog HDL实现-Verilog HDL CY7C68013 and FPGA implementation of the interface
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
13_usb_test
- fpga usb2.0 cy7c68013 黑金的板子(fpga usb2.0 cy7c68013)
CY7C68013固件程序 FPGA测试Verilog程序
- CY7C68013固件程序 FPGA测试Verilog程序(CY7C68013 firmware, FPGA test, Verilog)
ezusb_io_latest.tar
- CY7C68013实现FPGA控制的USB接口通信，已通过测试(CY7C68013 FPGA control to achieve the USB interface communication, has passed the test)