通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真,Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6

循环码纠错译码器，简单易学，十分适合初学者使用-Cyclic code error correction decoder, easy to learn, very suitable for beginners to use

The Decoder of differential cyclic code using in the broadcasting receiver.