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FPGA-based-DAC
- 用fpga实现的DA转换器，有说明和源码，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC cons
delsig
- Oversampling Delta-Sigma Data Converters
All_Digital_DC2DC_Converters_on_FPGA
- The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to imp
61EDA_D1116
- A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulat
analog-to-digitalconversionofthespecificationsandp
- 这份术语表定义了TI公司的delta-sigma、逐次逼近型和流水线模数转换器，并详细说明他们的规格和性能特点。-approximation register (SAR), and pipeline analog-to-digital (A/D) Converter specifications and performance characteristics. Although there is a considerable amount of detail in this docume
verilogsigma-deltaadc
- 用verilog编写的sigma-deltaADC的源程序。-code of verilog for sigma delta ADC
sndr
- 计算流水式模数转换器或者sigma-delta adc的SNDR-calculate SNDR of pipelined adc or sigma-delta adc
adc_spi
- dsp通过SPI接口数据采集 sigma-delta ADC采集程序-dsp through the SPI interface, data acquisition sigma-delta ADC acquisition program
delta-sigma
- 关于delta-sigma调制器的详细教程
delsig
- AD中用于调制解调的delta sigma一阶调制器-AD used for modulation and demodulation of the first order delta sigma modulator
dac
- Delta sigma DAC for use in FPGA includes Testbench
decimator
- Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
A-FPGA-Based-Delta-Sigma-DAC
- 用FPGA实现AD转换的代码,使用VHDL语言编写-A FPGA Based Delta-Sigma DAC
SDtoolbox
- delta-sigma 设计工具箱，可以进行调制器设计，数字滤波器设计等-design-box of delta-sigma ADC
sigma-delta-adc-example
- sigma-delta adc 示例代码-sigma-delta adc example
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略，∑-Δ DAC的内部仅由2个10位的二进制加法器，1个10位的锁存器和一个D触发器组成，用FPGA实现时只需耗费极少的逻辑资源，即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
LTC2440_1
- 一款具有 5ppm INL 和 5μV 偏移的高速 24 位无延迟增量累加 (No Latency ΔΣTM) ADC LTC2440的源代码-A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
sigma-delta-modulator
- 实现SIGMA-DELTA Modulator的veriolog代码-sigma-delta moudulator for RFPLL
filter loop
- sigma-deltaADC的环路滤波器设计FPGA实现(realise sigma-delta ADC and it filter)
delta-sigma
- 实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)