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verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
edge_detection
- edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
miller
- 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice
sobel
- verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
PCM30_Frame_Sync
- 本程序实现了PCM30的帧同步和失步检测，采用verilog编程，包含了工程文件。-This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
2FSK_decode
- 程序实现2FSK的解调，使用过零检测法，分为预处理模块和鉴频处理模块，Verilog语言，在modelsim仿真通过-2FSK Program for demodulation of zero-crossing detection method used, divided into pre-processing module and the discriminator processing module, Verilog language, adopted in the modelsim sim
jiancelvbo
- 滤波器加上功率检测的verilog语言，对于嵌入式研发人员有较大的帮助，由于能力有限，请多包涵-Filters with power detection verilog language for embedded developers have a greater help, as capacity is limited, like him indulgence
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
error-detection-device
- 使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。-Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has som
Desktop
- 频率检测，verilog hdl,单片机用C8051F120外部中断0。测量范围2Hz到9MHz-Frequency detection, verilog hdl, C8051F120 microcontroller with external interrupt 0. Measuring range 2Hz to 9MHz
Posedge-Detection-Circuit
- Verilog脉冲边沿检查，此代码包含完整的工程，利用quartus软件可以直接运行仿真。-Verilog edge of pulse examination, this code contains the complete engineering, quartus software can be used to directly run the simulation.
sequence_detector
- verilog之序列检测，vivado工程，使用状态机的方式检测任意长度的数据顺序，提供四个检测工程，并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides four detection project, and all w
verilog
- 自适应神经网络算法，用于障碍物检测，基于FPGA可综合实验-Adaptive neural network algorithm for obstacle detection, based on the FPGA can be integrated experiment
tnn7_code_201212141110
- 人脸检测与跟踪是一个重要而活跃的研究领域，它在视频监控、生物特征识别、视频编码等领域有着广泛的应用前景。该项目的目标是在FPGA板上实现实时系统来检测和跟踪人脸。人脸检测算法包括肤色分割和图像滤波。通过计算被检测区域的质心来确定人脸的位置。该算法的软件版本独立实现，并在matlab的静止图像上进行测试。虽然从MATLAB到Verilog的转换没有预期的那样顺利，实验结果证明了实时系统的准确性和有效性，甚至在不同的光线、面部姿态和肤色的条件下也是如此。所有硬件实现的计算都是以最小的计算量实时完成的
sw_debounce
- 脉冲边沿检测法的按键消抖程序，使用Verilog编写(Key edge dithering program with pulse edge detection method)
EDAC
- Error Detection and Correction
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
Verilog的边沿检测技术_设计源代码
- 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
crc_core
- 程序主要用来检测或校验数据传输或者保存后可能出现的错误。它是利用除法及余数的原理来作错误侦测的。(The program is mainly used to detect or verify data transmission or to save possible errors.It is an error detection using the principle of division and remainder.)