用VHDL语言实现数显时钟，devid200.vhd为分频模块，scan.vhd为LED扫描模块，timecount.vhd为计数模块-VHDL digital clock, devid200.vhd for frequency module, scan.vhd for LED scanning module, timecount.vhd for counting module

新来匝道穿上别人写的基于vhd的数字时钟很好大家看看啊，很规范的哦。-New ramp to wear someone else wrote vhd on the digital clock very well take a look at the ah, oh, very norms.

8.2 LED控制VHDL程序与仿真 本节分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。 1. 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd。 --功能：译码输出模块，LED为共阳接法。 --最后修改日期：2004.3.24。 -8.2 LED control and simulation of VHDL procedures introduced in this section of the LED using FPGA st

VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module