verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores

实验一 离散时间信号的时域表示 实验二 离散时间系统的时域表示 实验三 离散时间序列的傅立叶变换 实验四 Z变换 实验五 离散傅立叶变换 实验六 数字滤波器的结构 实验七 IIR数字滤波器设计 实验八 FIR数字滤波器设计 实验九 DSP实现-Experiment a discrete-time signal in the time domain representation Experiment two discrete-time time-domain r

LCMV optimization design array signal processing, Channelized receiver based on multi-phase structure, Nonlinear discrete system identification.