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divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
verilog-divider-code
- Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
gcd
- 这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
divider16
- 16位小数除法器verilog源码，可综合的，已经仿真过。-16bit fractional numeral divider verilog source
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
devider
- a divider design based on verilog language
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
divide
- It is n-bit sequential divider in verilog language
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
divider
- verilog divider hardware
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
frequency divider and testbench
- a frequency divider and test bench with simulation results
VERILOG
- 基础的几个verilog代码实现，讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)