Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5

Parallel Implementation of Fast Hartley Transform (FHT) in Multiprocessor Systems

面积和速度的互换是FPGA/CPLD设计的一个重要思想。乒乓操作、串并转换-The balance between area and speed is a important idea in the design of FPGA/CPLD. Ping-pong operation、the conversion between series and parellel