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ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
fifo-ram
- 采用Verilog语言描述的FIFO和双端口RAM源代码。
fifo
- 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。
同步FIFO设计
- 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
FIFO
- FIFO中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
VHDL
- 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
FIFO
- 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
RamFifoVHDL
- Ram Fifo Core VHDL file
FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta
- FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Synchronous FIFO
- 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writi