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verilog 128位 突发4. sdr fpga控制器,verilog 128 bit unexpected 4. sdr fpga controller
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verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
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一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
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SDRAM 控制器的Verilog代码
经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
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Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
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使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
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This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform.
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xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
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fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
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用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
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FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware descr iption language, the file contains a total of: hostcont.v, inc.h, pinout
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FPGA SDRAM控制器Verilog源码，通过测试-FPGA SDRAM VERILOG
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verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
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基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
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This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
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fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
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此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
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基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
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sdram的驱动开发，支持单字节读写，全页读写，自定义长度读写。(SDRAM drive development, support single byte read and write, full page read and write, custom length read and write.)
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基于FPGA的640*480的sdram项目，使用verilog语言，教学项目教学项目(The SDRAM project of 640*480 based on FPGA, the use of the Verilog language, the teaching project teaching project)
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