搜索资源列表
lpc21xx_watchdog
- 使用Keil for arm编译环境的LPC21xx的watchdog（看门狗）的工程示例程序，对使用LPC21XX的单片机开发人员有参考价值。-use Keil compiler for arm of the environmental watchdog LPC21xx (gates dog) project examples procedures, the use of SCM LPC21XX Developer reference value.
EX
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
1_LAB
- Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
100exampleofvhdl
- 100个VHDL例子，包括各种逻辑门、组合逻辑电路及时序电路-100 VHDL examples, including a variety of logic gates, combinational logic circuit and timing circuit
11
- 一个水闸水位控制程序，可根据水位的高低自动控制水闸的开关-A sluice water level control procedures, according to the level of the water level automatic control gates of the switch
vhdl_manygoodmodel
- VHDL例程集锦，有很多例子，从简单的逻辑例程到复杂的微操作系统和相关存储器。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinationa
BaseGate
- ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
74
- 7400 QUAD 2-INPUT NAND GATES 与非门 7401 QUAD 2-INPUT NAND GATES OC 与非门 7402 QUAD 2-INPUT NOR GATES 或非门 7403 QUAD 2-INPUT NAND GATES 与非门 7404 HEX INVERTING GATES 反向器 7406 HEX INVERTING GATES HV 高输出反向器 7408 QUAD 2-INPUT AND GATE 与门 7
GAL16V8
- GAL16V8可以实现基本门电路功能 CPUL语言编写-The basic logic gates implemented in GAL16V8
mux4x1
- mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case. the fastest model is the one implemented with the case code.
Ripple_Counter
- Ripple carry counter with 4 bit resolution implemented in behavioral VHDL. attaches as well is a jpg with the logic gates bock diagram. this is an asinchronous design.
Voltage_multipliers_with_CMOS_gates
- Voltage multipliers with CMOS gates
digital_logic_gates
- A graphic simulation of digital logic gates whitch can be used in DIGITAL DESIGN
Source
- 某公司安装了电子门，要设计门禁系统： 公司的雇员可以凭借密码、胸卡或指纹进入公司 计算机根据雇员的验证方式对其身份进行验证 管理员在监控室可以通过按钮直接开启电子门 访客可以按门铃请求进入，由管理员为其放行 管理员可以为新职员设置密码 -A company to install an electronic gate, to design access control systems: the company' s employees can rely on pas
BasicS
- an example HDL-Core with any basic gates.
vhdlprograms
- uploaded files include vhdl for basic gates.
Quadruple-2-Input-Exclusive-Or-Gates
- quadruple dual input exclusive or gates
Logic-gates-experiment
- 逻辑门实验，用于物理课程的讲解，使用的是光敏电阻和驻极体话筒作为光传感器和声音传感器，硬件比较简单。使用的是STC12C5A60S2单片机。里面可以实现所有的基本逻辑门演示功能。-Logic gate experiment, explain the physical course, using a photosensitive resistance and electret microphone as optical sensors and sound sensors, hardware is
Compiler for Quantum Processor Emulator using Toffoli gates
- Compiler for Quantum Processor Emulator (in FPGA), that uses Toffoli gates. Developed in C#