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I2C_slave_model
- 完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考 -integrity of the I2C slave model and spec are attached, want to use Verilog for the development of such transmission of reference
eeprom_i2c.tar.gz
- I2C EEPROM verilog simulation model,I2C EEPROM verilog simulation model
i2c_model.tar
- I2C EEPROM verilog simulation model
iic
- 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
i2c_24c64
- 基于verilog的i2c接口EEPROM 24lc64的测试程序，包括了eeprom的虚拟模型，实际在硬件上验证没问题，也可以通过modleism进行仿真(Verilog based I2C interface EEPROM 24lc64 testing procedures, including the virtual model of EEPROM, the actual hardware verification is no problem, you can also simulate