verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second

使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)