搜索资源列表
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
jk_ff
- 这是我自己写的一个关于JK触发器的VERILOG 程序。-This is one I wrote it myself on the JK flip-flop process of VERILOG.
fgdfg222222
- 设计本课题时构思了两种方案：一种是用以AT89C2051为核心的单片机控制方案；另一种是用以74LS112双JK触发器构成的数字逻辑电路控制方案。考虑到单片机方案原理复杂，而且调试较为繁琐，所以本文采用后一种方案。-When the subject of the design concept of the two programs: one is for the AT89C2051 MCU as the core control program the other is for the 74L
jkff
- JK flip-flop is implemented using VHDL
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
JKdff
- 基于VHDL语言设计的边沿JK触发器，及相应的仿真波形-VHDL language design based on the edge of JK flip-flop, and the corresponding simulation waveforms
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
jkandTflipflop
- this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
jishuji
- 将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成一个FPGA芯片中模拟其功能，并研究其相互转化的方法。-The basic RS flip-flop, synchronous RS flip-flop, integrated JK flip-flop, D flip-flop while a FPGA chip analog integrated function, and to study their mutual transformation method.
jk
- 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
JK
- JK触发器的功能实现，采用VHDL编程，可以下载到FPGA中进行演示-JK flip-flop implementation of function, using VHDL programming, you can download a presentation to the FPGA,
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
JK
- 使用jk触发器来实现CMI码的编译码，延时小，操作方便-Using jk flip-flop to achieve the CMI code encoding and decoding, the delay is small, easy to operate
jk
- 基于quartus2的jk触发器设计，内含源码和仿真图-Jk flip-flop design based on the quartus2, containing source code and simulation diagram
vhdl-code-for-jk-flip-flop
- vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
JK
- 带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器-With reset terminal, set end delay the 15ns CP' s response to the falling edge of the JK flip-flop
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language