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gongchengsheji-477
- 基于logmap算法的vhdl的实现。 通信系统的log—map算法数字vhdl的实现-logmap algorithm based on the achievement of VHDL. The communication system log-map algorithm to achieve the number of VHDL
110detector_lab
- 一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
jiaotongdengcodes
- 实例制作的一个有关交通灯的VHDL代码，从各模块到顶层文件的代码一一列出，详细周到，附带仿真波形图和芯片管脚锁定的相关内容，绝对物超所值。-produced an example of the traffic light VHDL code, from the module to the top of the document sets out a code on January 1, thoughtful details, fringe simulation waveform map and
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
wavegenerator
- 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verif
CAN_design
- 实现can总线的硬件布线图，在protel上直接打开即可，按此图的实物板已制出，可确保无误。-The realization of the hardware can bus wiring diagram, in Protel can directly open, this physical map has already been produced to ensure accuracy.
mux21a
- 2选1多路选择器的VHDL完整描述，即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete descr iption of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is th
bb
- CPLD可编程逻辑芯片上实现信号发生器的方法和步骤，系统采用自顶向下的设计方法，以硬件描述语言VHDL和原理图为设计输入，利用模块化单元构建系统。-CPLD programmable logic chip Signal Generator methods and steps system uses top-down design approach to hardware descr iption language VHDL and principles of map design input,
LEDVHDL
- LED控制VHDL程序与仿真，有源程序和仿真图，希望对大家有用-VHDL program LED control and simulation, there is source code and simulation map, useful for all of us hope
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
butterfly
- 计算离散傅里叶变换的一种快速算法,简称FFT。快速傅里叶变换是1965年由J.W.库利和T.W.图基提出的。采用这种算法能使计算机计算离散傅里叶变换所需要的乘法次数大为减少,特别是被变换的抽样点数N越多,FFT算法计算量的节省就越显著。 -Discrete Fourier transform calculation of a fast algorithm, referred to as FFT. Fast Fourier Transform in 1965 by JW Cooley an
FSK_modulation_VHDL
- FSK调制的VHDL程序，有详细注释，并在最后附上仿真图，方便理解和验证。-FSK modulation of the VHDL program, detailed annotations, and attach a simulation of the final map, to facilitate understanding and validation.
FSK_demodulation_VHDL
- 基于FSK解调的VHDL程序，有详细的注释说明，并在最后附上仿真图，便于理解和验证。-VHDL-based FSK demodulation process, a detailed explanatory notes, and attached in the final simulation map, easy to understand and verify.
ys
- 两路单极性HDB3+和HDB3-信号，经映射模块后完成单极性到双极性信号的数字转化，该模块由设计文件ys.v完成。由于映射后得到的是双极性归零码，通过该模块得到双极性非归零码。该模块由设计文件delay.v完成-Two unipolar HDB3-signals HDB3+, and by the mapping module to complete unipolar to bipolar signal digital conversion, the module completed by th
turbocodes_latest.tar
- Turbo Codes - max lop map algorithm
pwm_ok_PWM
- 用VHDL实现占空比任意可调的PWM产生器。（程序逐行注释），有仿真图。PWM,即Pulse-Width Modulation 脉宽调制，常用于电机的控制中。-Using VHDL adjustable duty cycle of PWM generator. (Progressive program notes), a simulation map. PWM, i.e. Pulse-Width Modulation PWM, used to control the motor.
spatiotemporal_computing_core
- 用VHDL实现时空混沌：耦合映像格子(CML)-The spatiotemporal chaos of coupled tent map lattice implemented by VHDL.
fu_dian_chu_fa
- VHDL浮点除法运算，VHDL浮点数除法，源码，含仿真图 -VHDL floating point division, source code, including simulation mapVHDL floating point division, source code, including simulation map
VHDL
- dsp-2812VHDL的源代码，里面有map文件、等等 有用的知识-dsp-2812 VHDL source code, there are map files, etc. Useful knowledge
project.map
- D Flip Flop for Single Bit Store