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05_UsingAccelWare
- This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each
MATLAB_sg_IP.rar
- 使用MATLAB为System Generator for DSP创建IP,The use of MATLAB for System Generator for DSP to create IP
tes_amp_80_0314
- 基于dsp builder的数字下变频器，IP核做的-digital down converter,degigned in matlab
MIF_file_of_Sine_Wave_Generator
- 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to t
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
fft-ip-core
- 通过调用ISE中的fft IPcore实现了fft计算，输入数据通过textio从文本文件读入，处理后的数据再读入文本中。由于数据精度问题，与MATLAB计算的结果存在一定的误差-By calling the ISE of FFT IPcore implements the FFT computation, the input data through textio read a text file, after processing the data to read the text aga
iir_2n_ip_float_demo
- 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
xapp794
- 里面分为八个实验，一步一步教你使用system genertor for dsp 生成能供vivado使用的IP核文件。(It is divided into eight experiments, which teach you to use system genertor for DSP step by step to generate IP core files that can be used for vivado.)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve