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目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
MDCforTIMING
- 飞思卡尔HCS12里的定时和计时的方案,列出例子,以供参考.MDC,这个比较好用,精确,容易计算-Freescale HCS12 s timing, and timing of the program, listing examples for reference. MDC, this relatively easy to use, accurate, easily calculated
MDC_FOR_TIMING
- 用飞思卡尔HS12系列单片机生成的定时程序，使用MDC方式作为定时器-Freescale HS12 Series MCU with the generated timing procedures, using the MDC as a means to the timer
MDC-FOR-TIMING
- 飞思卡尔单片机的模数递减定时器，注意是递减-Freescale microcontroller modulus decreasing timer, attention is decreasing
LPC176x-web
- keil 源文件，包含tcpip协议栈,easyweb sever-This project is migrated from Keil MCB1700 Demo code. It can run at Keil MCB1700 board with LPC17xx. Example functionality: - Clock Settings: - XTAL =
tugedafinal
- 使用Verilog HDL语言写的关于实现对ADC、MDC控制的程序，个人使用Quartus 7.2,在上面进行过仿真，暂时还没有发现问题-Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
mdc
- 实现对MDIO通信接口的MDC主机时钟进行整形，输出占空比50 的时钟方波-MDIO communication interface to achieve the MDC host clock shaping, the output duty cycle of 50 of the clock Fang Bo