搜索资源列表
IO-Model
- HE48R/E05A 实现I/O模式的工作原理-HE48R/E05A realize I / O model of principle
MXIC-SPIFlash-Model
- Verilog based simluation model for MXIC SPI Flash.
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
LCD320240_VC.rar
- Proteus的元件模型,按照LM2068的LCD屏做的,项目上用到这屏,可是Proteus没有,所以做了一个.,Proteus component model, in accordance with LM2068' s LCD screen to do the project on the need to invoke the screen, but Proteus does not work, so one.
eeprom_i2c.tar.gz
- I2C EEPROM verilog simulation model,I2C EEPROM verilog simulation model
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
8x8LED
- 刚做好的led屏模拟有程序，8点阵，附有Proteus仿真模型-Just do the led screen simulation procedure, 8 matrix, with Proteus simulation model
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
micron_sdram_simulation_model
- micron各种规格的SDRAM的仿真模型及详细设计资料，基于verilog语言。-micron variety of SDRAM simulation model and detailed design information, based on the verilog language.
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
tsmc_018um_model
- tsmc 180nm cmos模型,可以应用于hspice等仿真软件-tsmc 180nm cmos model, which can be used in hspice.
windspeedsimiulaition
- 采用自回归滑动模型进行风速时程的模拟，本程序主要是针对的Davenport谱-Using autoregressive moving model of the simulated wind speed time history, the program is mainly directed against the Davenport spectrum
model
- svpwm 模型 可用于三相PWM整流 电机控制，参数可调-svpwm model can be used for three-phase PWM rectifier motor control, parameter adjustable
Nokia6610LCD-Proteus_VSM_Model
- Nokia 6610 LCD (Proteus VSM Model) 在电脑上直接模拟C51调试Nokia 6610 LCD 显示屏-Nokia 6610 LCD (Proteus VSM Model) directly in the computer simulation to debug Nokia 6610 LCD screen C51
M25P32_VG_12_50MHZ
- Serail Nor Flash Memory Model
i2c_model.tar
- I2C EEPROM verilog simulation model
Verilog-Round-Robin-Arbiter-Model.tar
- Verilog Round Robin Arbiter Model