搜索资源列表
moore
- Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.
MOORE
- 状态机设计，用VHDL进行MOORE型状态机的设计。原程序以及波形图
moore
- moore状态机,综合已通过，可放心使用！正式版。
moore state_machine
- 这是一个moore状态机的典型程序，供初学者参考-This is a typical state machine moore procedure reference for beginners
moore1
- moore 状态机的一个简单的事例，初学者很好的地实例！-moore state machine of a simple example for beginners to very good example!
moore
- 主要介绍moore状态机的详细功能及应用，程序是用hdl写的！-Moore state machines are introduced in detail the function and application of the procedure is written hdl!
example2
- 状态机一般分为三种类型： Moore 型状态机：次态=f(现状，输入)，输出=f （现状）； Mealy 型状态机：次态=f(现状，输入)，输出=f （现状，输入）； 混合型状态机。 -State machine is generally divided into three types: Moore-type state machine: sub-state = f (the status quo, input), output = f (status) Mealy
fsmmoore
- vhdl CODE FOR moore MODEL AND mux
vhdl_pgms
- Program for Counter, mealy machine, moore machine, ones counter, seven segment with zero blanking and shift register in VHDL.
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
mealymoore
- verilog project for mealy and moore
moore
- vhdl simulation code for moore machine
moore
- 摩尔有限状态机的例子很好的，实验读写控制-an example of FSM of moore
moore
- MOORE fsm source code in vhdl, implemented on fpga
moore
- 此代码利用状态机的思想实现moore型的时序逻辑电路。-This code using state machine thought realize Moore type of sequential logic circuit
Moore
- VerilogHDL语言实现的Moore 序列检测器-VerilogHDL language of Moore sequence detector
moore
- 状态机 基于xilinx ise硬件描述语言-moore VHDL
moore
- moore状态机，quartusii上仿真通过-moore state machine
moore
- FPGA实现moore状态机，适合新手学习，开发环境Q2-FPGA implementation moore state machine, suitable for novice learning, development environment Q2
Vending-Machine-using-Moore
- Vending Machine simulation using Moore sequence