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FPPG_CPLD_VHDL
- Polish documentation of FPGA, CPLD and VERILOG. Many examples and datasheets.
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
caculator
- 基于博创ARM2410-SforUCOS平台的计算器，利用逆波兰式算法，可以实现键盘和触摸屏操作，可以实现加减乘除、括号、删除和清屏功能-Borch-based platform, ARM2410-SforUCOS calculator using Reverse Polish Notation algorithm can achieve keyboard and touch screen operation, addition and subtraction multiplication an
PI_(BuilderCPPMathProgram-pl)
- Program written in Builder C++. It counts Number PI to as many digits after dot, as user wants (If the computer has enaugh RAM and user wants to wait) Use interface is written in Polish, but it s very simple. I used alghoritm by Taylor & Maclanrin (I
infix_to_p207456792007-(1)
- POLISH NOTATIONS USE