搜索资源列表
State.Machine
- State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
LCD.rar
- 有限状态机的设计——LCD显示控制实验，用VHDL编写程序，整片报告,Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
Drive-ADS8365-state-machine
- 驱动ADS8365状态机,Quartus II Verilog-Drive ADS8365 state machine, Quartus II Verilog
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
fsm
- 有限状态机工作原理、设计方法、步骤等精要说明-Finite state machine working principle, design method, such as Essentials of steps to explain
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
VHDL
- 各种有限状态机的设计。 VHDL源代码。 -All kinds of finite state machine design. VHDL source code.
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
VHDLprogram
- 含有各类寄存器，AD和DA转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
state
- 米勒解码器的状态转换模块。用verilog语言编写，ISE为开发环境-Miller decoder module of the state transition
state
- verilog语言编写的miller解码的状态转换模块，这个是仿真成功了的-verilog language miller decoding module state transition, this is the successful simulation of the
mmi
- 手机mmi状态机，包括打电话、发短信、SAT-State machine of mmi of mobilephone, it s including Call, SMS, SAT etc.
telephone
- 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
State-Machine
- 这是个人整理的11篇有关状态机的资料，很有用。-This is a personal order of 11 information on the state machine, very useful.
classic-state-machine-C-code
- 4种经典状态机C代码，代码详细，可供学习者参考-Four kinds of classic state machine C code
Finite-state-machine
- 有限状态机在嵌入式软件中的应用 简述了有限状态及的基本概念和传统理论，提出了利用有限状态机进行程序设计的基本思想。-Finite state machine in the embedded software Finite state and the basic concepts and theories, the basic idea of the finite state machine programming.
State Machine
- VHDL State machine code