基于单片机的数字时钟，实现精确计时，并且可对时间各位数进行手工调整（即每按一次按钮，相应位数的数字增加1。）-Based on single-chip digital clock, accurate time, and you can time the number of manual adjustments (that is, every time the button, the corresponding median increase in the number 1.)

十进制计数器既可采用QuartusII的宏元件74160，也可用VHDL语言设计。在项目编译仿真成功后，将设计的十进制计数器电路设置成可调用的元件cont10_v.sym，用于4位十进制计数器的顶层设计。-Decimal counter can use QuartusII macro components 74160, also available VHDL language design. After the success of the project compiled simulation

六位十六位进制数可逆循环计数器、七段译码器设计，完全有VHDL语言设计，生成SYM文件后，设计top.gdf文件，赋好管脚下载到altera芯片上执行。-Sixteen decimal six reversible cycle counter, seven-segment decoder design, fully VHDL language design, build SYM files, design top.gdf file, assign a good pin downloaded to

128位加法器优化设计：64位加法运算+2-1多路选择器。并在关键路径上添加寄存器，降低延迟。 testbench可以测试优化的效果，在ISE中做过综合，能跑到200+MHz-128-bit adder optimization design: 64-bit adder+ 2-1MUX. In the key path, there are regs to improve the performance and reduce the delay time. you use the tes