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ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
designcompiler
- its a descr iption collected to learn synopsys design compiler-its a descr iption collected to learn synopsys design compiler...
ASIC-SYNOPSYS
- 芯片设计综合经典书籍 design compiler primetime-asic synthesys
ASGN-1-2a3.tar
- VHDL MODELSIM FUNCTIONAL SIMULATION AND SYNTHSIS USING SYNOPSYS DESIGN COMPILER
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize
DC Synopsys Workshop
- Design Compiler 工作台教程文档 操作手册(Design Compiler Workshop Tutorial Document Operation Manual)