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Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
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Tutorial from VCS to IC Compiler for ASIC design using synopsys tool.
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its a descr iption collected to learn synopsys design compiler-its a descr iption collected to learn synopsys design compiler...
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芯片设计综合经典书籍
design compiler
primetime-asic synthesys
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VHDL MODELSIM FUNCTIONAL SIMULATION AND SYNTHSIS USING SYNOPSYS DESIGN COMPILER
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GCD CALCULATOR (ESD book figure 2.11)
Weijun Zhang, 04/2001
we can put all the components in one document(gcd2.vhd)
or put them in separate files
this is the example of RT level modeling (FSM + DataPath)
the code is synthesize
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Design Compiler 工作台教程文档 操作手册(Design Compiler Workshop Tutorial Document Operation Manual)
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