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emiftofifo
- This program uses the HF flag of a FIFO to trigger reads, guaranteeing that the FIFO is never blocked for the writer, giving high throughput for the reader (bursts of D/2 = 128) and guaranteeing that the the reader will not be stuck in the top half o
WirelessNetworkingLab106RateControl
- This exercise is aimed at exploring how rate control and adaptation of carrier sense threshold can affect spatial reuse (and hence aggregate throughput) in a multi-hop network.
gpioAD7888.rar
- AD7888的调试程序,串行模式，四输入端，十二位，适合直流信号,The AD7888 is a high speed, low power, 12-bit ADC that operates from a single 2.7 V to 5.25 V power supply. The AD7888 is capable of a 125 kSPS throughput rate.
fff
- wiMAX Throughput Evaluation of Conventional Relaying Pavel Mach1, Robert Bestak1 1 Department of Telecommunications Engineering, Faculty of Electrical Engineering, Czech Technical University, Technicka 2, 166 27 Prague 6, Czech Republic {
hilbert_transformer_latest.tar
- The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hil
VRS51L3074
- VRS51L3074是一款嵌入非易失性 FRAM存储器的8051MCU。该器件8KB真正的非易失性随机存储器映像到VRS51L3074的XRAM存储寻址空间上充分发挥其快速读写以及读写寿命无限的特点。单周期8051处理器 内核可以提供高达 4O MIPS的吞吐量，并且与标准8051s指令兼容。 -VRS51L3074 is an embedded non-volatile FRAM memory 8051MCU. The device truly non-volatile 8KB RAM VRS
mobility
- Wireless range extenders or wireless repeaters can extend the range of an existing wireless network. Range extenders can be strategically placed to elongate a signal area or allow for the signal area to reach around barriers such as those created in
OmapAnalysis
- OMAP System DMA Throughput Analysis
debussy53
- Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput s
SoftwareTestingWhitePaper
- 测试在所有的软件开发过程中都是最重要的部分。在软件开发过程中，一方面要求 我们通过测试活动验证所开发的软件在功能上满足软件需求中描述的每一条特性， 性能上满足客户要求的负载压力和相应的响应时间、吞吐量要求；另一方面，面向 市场和客户，开发团队还要满足在预算范围内尽快发布软件的要求。-Test all the software development process is the most important part. In the software development proc
zlg
- P89V51RB2/RC2/RD2 是一款 80C51 微控制器，包含 16/32/64kB Flash 和 1024 字节的数 据RAM。 P89V51RB2/RC2/RD2 的典型特性是它的X2 方式选项。利用该特性，设计工程师可使 应用程序以传统的 80C51 时钟频率（每个机器周期包含 12 个时钟）或X2 方式（每个机器 周期包含6 个时钟）的时钟频率运行，选择X2 方式可在相同时钟频率下获得2 倍的吞吐量。 从该特性获益的另一种方法是将时钟频率减
ADPCMCodec
- The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices [1]. ADPCM is a transformation that encodes 16-bit audio as 4 bits (a 4:1 compression ratio).
c8051f326
- C8051F326/7 Silicon Laboratories Full Speed USB, 16 kB Flash MCU Family 對CIP-51 Microcontroller Core各個Pin的每個bit代表功能的詳盡說明-C8051F326/7 Silicon Laboratories Full Speed USB, 16 kB Flash MCU Family 1. System Overview 1.1. CIP-51 Micro
parallel_CRC_code
- CRC Generation can be done by using PARALLELISM. Efficient method to calculate CRC in less time. By using more hardware for parallel CRC and obtaining more latency and throughput.
h
- WiMAX Throughput Evaluation of Conventional Relaying Pavel Mach1, Robert Bestak1 1 Department of Telecommunications Engineering, Faculty of Electrical Engineering, Czech Technical University, Technicka 2, 166 27 Prague 6, Czech Republic {
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
23984860-VLSI-Design-of-Turbo-Decoder-for-Integra
- In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo co
Code
- computes the throughput in a cognitive radio network
High-Speed-FFT
- 优秀硕士论文，课题采用现场可编程门阵列((FPGA)，设计实现了一种超高速FFT处理器。目前，使用FPGA实现FFT多采用基2和基4结构，随着FPGA规模的不断扩大，使采用更高基数实现FFT变换成为可能。本课题就是采用Alter的Stratix II芯片完成了基16-FFT处理器的设计。在设计实现过程中，以基2-FFT搭建基16-FFT的运算核，合理安排时序，解决了碟形运算、数据传输和存储操作协调一致的问题。由于采用流水线工作方式，使整个系统的数据交换和处理速度得以很大提高。本设计实现了4096
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA