搜索资源列表
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
UART
- 简易UART程序 verilog 描述-Simple UART procedure described in verilog
UART
- 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
RS232
- It s combination logic for UART. edited in verilog-HDL
RS232
- It s combination logic for UART. Edited in verilog-HDL.
uart
- 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
Uart
- UART source code in verilog
s24_uart
- 这是一个串口通信协议，有详细的说明，欢迎下载！-This a code of uart in verilog ，describled in detail,welcome to download!
uart-in-verilog
- develop uart using verilog language-develop uart using verilog language...
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
uart
- uart receiver, transceiver code in verilog
LIFO_Spartan3
- The code for a LIFO in verilog
UART
- 用Verilog实现的全局异步接收发送机，在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
c8_uart
- UART program in verilog
UART-master
- FPGA Based UART in Verilog