介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided in

本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.

VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.

四位无符号二进制除法器的设计,这是整个的工程文档，应该对大家有用-4 unsigned binary division Design

介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。-A programmable logic device FPGA and VHDL design of the 32 divider. The divider can be achieved not only symbolic arithmetic, unsigned op.