搜索资源列表
verilog实现ALU的源代码
- verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
CAN协议控制器的Verilog实现
- CAN协议控制器的Verilog实现
verilog实现串并转换
- verilog实现串并转换的源代码
GPS去载波verilog实现
- 该源码用verilog实现gps信号的去载波过程
直方图统计的Verilog实现
- chengxu:直方图统计的Verilog实现，大家可以共同学习
树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
shift_register.用Verilog实现的移位寄存器
- 用Verilog实现的移位寄存器，可以实现左移、右移等功能,Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
任意维矩阵求逆的verilog实现方式
- verilog 任意维矩阵求逆的verilog实现方式,Verilog arbitrary-dimensional matrix inversion methods to achieve the Verilog
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
cpu_lynn
- Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
canbus
- canbus verilog实现，原代码文件-canbus verilog implementation, the original source document
verilog-counter
- 利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
16bitADC
- verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
dispenser-verilog-implement
- 用verilog实现自动售货机的买卖过程，其中包括投了钱却不想买东西，投了太多的钱等特殊情况-dispender implement by verilog it is mainly for verilog beginner.
Verilog-dds
- 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
斐波那契数列Verilog实现
- 斐波那契数列Verilog实现
CMA
- 用Verilog实现FSE-CMA算法，分为四个模块，一共迭代8次(Implementation of FSE-CMA algorithm with Verilog)