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串口verilog源代码
- 串口UARTverilog源代码。包括控制模块、收、发模块。程序全，功能简洁，包含Q2工程
串口通信收发模块
- verilog编写的串口通信的接收模块和发送模块，经过仿真有效
RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
SPI_verilog_vhdl.rar
- SPI串口的内核实现（分别使用verilog和vhdl语言描述的）,The core of the realization of SPI serial port (using Verilog and VHDL language descr iption of the)
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
标准的串口通讯设计VHDL
- 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
UART_VHDL_Verilog_Lattice
- 本压缩包中含有串口程序的VHDL,Verilog，Lattice三种版本的代码，均已实现。在压缩包中，含有非常详细的串口的实现规格。各种版本的代码中，含有完成的源文件，测试文件，模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
uart_verilog
- UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginn
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xx
dct01
- Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
usartV1.2
- 基于Verilog实现串口通讯，通过串口调试助手可测试(Serial communication based on Verilog, through the serial debugging assistant can test)
IIC读写EEPROM发送到PC串口
- 能实现用IIC读EEPROM并且将读取的数据通过串口发送到PC端，以及在PC端通过串口发送数据给FPGA，再利用IIC将数据写入EEPROM(The program can realize that FPGA read the data from EEPROM by IIC and then send it to PC by UART,and that PC send the data to FPGA by UART and then write the data to EEPROM by
uart_ip
- 实现串口通信模块设置，包括频率分频、波特率产生、接口时序要求(Implementation of serial communication module settings, including frequency division, baud rate generation, interface timing requirements)
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)