搜索资源列表
crc16_8bit.v
- 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块
verilog
- 一个桶形移位寄存器的.v文件，含testbench
verilog
- 一个简单状态机的.v文件，含testbench
resource2.v
- verilog描述寄存组合电路 很不错
Verilog&Vhdl混语言对SDRAM的控制源代码
- Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
若干74HCxxx的Verilog源码。
- 包括：74HC85、74HC138、74HC161、74HC151、74HC373 74HC4017、74HC238、74HC194等器件的Verilog编码实现。为.V文件，也可直接用记事本等打开。
SPIsend.rar
- Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！,Verilog HDL programs, Internet find SPI program, vspi.v this very useful progra
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
wm8731_zhengxianbo
- 讲诉了如何编写VERILOG程序通过DE2开发板的wm8731芯片产生正弦波-Talk about how to write VERILOG v. procedure DE2 development board wm8731 chip generated sine wave
Verilog-HDL-code
- verilog 经典例子的源码 非常适用于初学verilog的朋友们-classic example of verilog source code
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
clock
- verilog program for real time clock.. select the .v file to view the code.
LIP1733CORE_system_vbus_arbiter
- Verilog V Bus arbiter module
DAC-use-verilog
- 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral descr iption
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
v
- statistical signal processing,verilog
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)