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IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE
- IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
IEEE_Verilog_2001
- 原版IEEE verilog/VHDL 2001标准。-IEEE verilog/VHDL 2001
FPGAREAL
- 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems.
Verilog
- 很不错的Verilog 书籍 ，包括ieee标准和黄金指南-Very good Verilog books, including ieee standards and Gold Guide
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
iverilog-0.9.2
- iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
ofdm
- ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
IEEE.Standard.Verilog.Hardware.Description.Languag
- IEEE Standard Verilog Hardware Descr iption Language-IEEE Standard Verilog Hardware Descr iption Language(
emiraga-ieee754-verilog-b7a63aa
- IEEE 754 floating point
Introduction-to-Verilog
- Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n
IEEE-standard-Verilog-HDL1364-2001
- verilog 硬件描述语言 golden版-verilog hardware descr iptor language golden version
verilog-RTLevel-Synthesis
- 本章详细的分析了寄存器传输级综合，ieee最新标准-IEEE Standard for Verilog® Register Transfer Level Synthesis
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
IEEE-standard-Verilog-HDL
- IEEE 标准 Verilog 硬件描述语言，这是IEEE 制订的verilog 标准参考文档-IEEE Standard for Verilog Hardware Descr iption Language
Prentice---Verilog.HDL_A.Guide.to.Digital.Design.
- Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented i
Verilog-2005
- IEEE的英文版VERILOG的教程，里面包括了所有使用方法，很好用-IEEE s English version the VERILOG of tutorials will be English friends can see
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
IEEE Standard for Verilog 2005
- IEEE Standard for Verilog 2005
IEEE Standard for Verilog 2005
- this book introduces the use of Verilog HDL.